This invention relates to semiconductor devices, and for example, is a technique applicable to a semiconductor device in which a first semiconductor chip and a second semiconductor chip are stacked over a wiring board.
One of the methods for packaging a plurality of semiconductor chips over a wiring board employs stacking a second semiconductor chip over a first semiconductor chip. Japanese Unexamined Patent Publication No. 2005-183934 discloses a technique of coupling a second semiconductor chip to a first semiconductor chip through bumps.
On the other hand, a method for coupling a semiconductor chip to another semiconductor chip by using through-silicon vias is under study. Through-silicon vias are provided so as to pass through a substrate of the semiconductor chip along the thickness of the substrate. For example, a method disclosed in Japanese Unexamined Patent Publication No. 2011-243724 includes stacking memory chips, each having through-silicon vias formed therein, and coupling these memory chips using the through-silicon vias.
In Japanese Unexamined Patent Publication No. 2011-243724, the lowermost memory chip is coupled to a wiring board through solder bumps. Around the lowermost memory chip, a frame-like metal member is provided so as to enclose the memory chip. In addition, a metal substrate is mounted over the uppermost memory chip with an adhesive member therebetween. The frame-like member in the publication is provided in order to increase the rigidity of the wiring board.